Research and Experience

Research Interests

Overcoming the limitations of Si-CMOS and Von Neumann architectures through multi-layered optimizations of the computer system hierarchy.

• Accelerating large-scale emerging applications such as deep learning recommendation models, genome assembly, and large language model (LLM)

• In/Near-memory processing

• Scalable and heterogeneous memory systems

• Emerging beyond Si CMOS devices

• Compiler optimizations

Publications

[1] Heewoo Kim, Sanjay Singapuram, Haojie Ye, Joseph Izraelevitz, Trevor Mudge, Ronald G. Dreslinski, Nishil Talati, “NMP-PaK: Near-memory processing acceleration of scalable de novo genome assembly,” ISCA (2025) [preprint] 

[2] Mingyao Shen, Suyash Mahar, Heewoo Kim, Joseph Izraelevitz, Steven Swanson, "AutoSSD: CXL-enhanced autonomous SSDs for low tail latency," HPDC (2025)

[3] Heewoo Kim, Haojie Ye, Trevor Mudge, Ronald G. Dreslinski, Nishil Talati, “RecPIM: A PIM-enabled DRAM-RRAM hybrid memory system for recommendation models,” ISLPED (2023) [link]

[4] Heewoo Kim, Javad Bagherzadeh, Ronald G. Dreslinski, “SiC processors for extreme high-temperature Venus surface exploration,” DATE (2022) [link]

[5] Heewoo Kim, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, Ronald G. Dreslinski, “A survey describing beyond Si transistors for non-experts, and exploring their implications for future processors,” ACM Journal on Emerging Technologies in Computing Systems (2021) [link]

[6] Ugo Otuonye, Heewoo Kim and Wei D. Lu, “Ge nanowire photodetector with high photoconductive gain epitaxially integrated on Si substrate,” Applied Physics Letters (2017) [link] 

Research In Progress

Enabling Cost-Effective LLM Inference via Near-Memory Processing on Mid-Tier GPUs

• PI: Professor Joseph Izraelevitz

AUTOPRUNE: A Stochastic Candidate Pruning Strategy for Souper

• PI: Professor Joseph Izraelevitz, Professor Tamara Lehman

Industry Experience

Intel Corporation, Remote (Jul. 2021 to Oct. 2021)

• Graduate student intern in Xeon performance team

• Conducted the cache size sensitivity study of future Xeon processors with performance model simulation.

Merit-Based Scholarships

Kwanjeong Educational Foundation Scholarship (2017 – 2021)

Jeongsong Cultural Foundation Overseas Scholarship (2015 – 2017)

National Science and Engineering/Humanities Scholarship (2009 – 2015)

Teaching Experience

ECEN 3593: Computer Organization - University of Colorado (2025 Spring)

• Main instructor

EECS 314: Electrical Circuits, Systems, and Applications - University of Michigan (2023 Fall)

• Leading the discussion and experiment lab sessions as a graduate student instructor